To improve the bit density of a non-volatile semiconductor memory device such as a NAND flash memory, lamination of memory cells has recently drawn attention because the miniaturization technology is approaching its limit. One proposed technology is a stacked NAND flash memory including a vertical transistor in the memory cell. The stacked NAND flash memory includes a memory string and select transistors provided at both ends of the memory string. The memory string includes a plurality of memory cells connected in series in the laminate direction.
In the stacked NAND flash memory, with the increase of the memory density due to the advance of miniaturization and with the increase of the number of memory transistors connected in series in one memory string, less current flows during the read operation, thus increasing the possibility of misreading.